1. Field of the Invention
The present invention is directed in general to the field of integrated circuit testing. In one aspect, the present invention relates to a system for testing different scan-based circuit componentry and/or logic that are located in a single chip.
2. Description of the Related Art
Complex very large-scale integrated circuits contain very large numbers of logic circuits that require extensive testing. In order to mitigate the complexity of the testing required, scan-based designs have been implemented. For example, level sensitive scan design (LSSD) test and diagnostic techniques are often used with VLSI chip designs that provide certain test attributes and features that make it attractive, particularly in situations where test time is not a big issue, and ease/simplicity of design is more important. In addition, general scan design (GSD) techniques are commonly used to test and diagnose circuit designs, especially in situations where high speed scan rates are desired that can not be provided by LSSD techniques. Where both GSD logic and LSSD logic are contained on the same circuit, such as can occur with systems-on-chip applications, testing problems can arise since the components designed using GSD techniques need to interface with components designed using LSSD methods. While the testing of GSD components can be carried out separately from the testing of the LSSD components, such separate testing cannot be applied in circuit designs where there are signals crossing back and forth between the LSSD logic and GSD logic because the logic for generating, sending and/or receiving these signals cannot be tested either by the standard LSSD methodology (since GSD logic is involved) or by the standard GSD methodology (since LSSD logic is also involved). Prior attempts to address this problem have proposed a special hybrid test mode for testing the boundary logic. In the hybrid test mode, clocks are fired in the following sequence; 1) a_clk in LSSD domain, 2) a single clock edge in the GSD domain, 3) b_clk in the LSSD domain. This hybrid test mode of operation adds extra complexity and cost into the test model creation, test vector generation and potentially the test procedure itself. In addition, the test tools and test models for both LSSD and GSD logic have to support an alternate mode of operation, and the chip test control unit must also provide the ability to run in this hybrid mode.
There are also timing problems associated with high-speed scan operation of integrated circuits in LSSD design. The timing problems arise because the LSSD clock signals (a_clk and b_clk) typically have varying latencies across the chip. To ensure complete non-overlap of the scan clocks and adequate pulse width for scan operation, these scan clocks are typically operated only at relatively low frequencies, with a generous margin between the falling edge of one clock (a_clk or b_clk) and the rising edge of the opposite clock (b_clk or a_clk). Prior attempts to address this problem have proposed local clock signal generation systems which use local clock buffers located at different points on the chip to generate local scan clock signals directly from the chip global clock (which is already designed as a low-skew timing reference for all circuits on the chip), thereby reducing timing differences or skew. However, these solutions, such as described in U.S. Pat. No. 6,825,695, are compatible with only one type of scan-based design (e.g., GSD), and are not compatible with other types of scan-based design (e.g., LSSD).
Accordingly, there is a need for an improved system and methodology for testing different scan-based circuit componentry and/or logic that are located in a single chip. In addition, there is a need for a local clock generation system that can be used with different types of scan-based designs on a single chip to reduce timing skew between local clock signals. Further limitations and disadvantages of conventional solutions will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.